In an integrated circuit, each bit of dynamic data is stored in a tiny circuit called a memory cell including an access transistor and an associated capacitor. Information or data is stored in the cell in the form of a charge on the capacitor. In the cell, the gate on the transistor is connected to a “wordline,” and the source of the transistor is connected to a “bitline.” The drain of the transistor is connected to the associated cell capacitor (with the other node of the capacitor connected to the ground or Vcc or Vcc/2). When both the wordline and the bitline are brought to high voltage and the gate-to-source voltage (Vgs) is high enough, the transistor is on and charge can flow to the capacitor. If the capacitor initially has no charge (stored 0) then charge flows into the capacitor, but if the capacitor initially is charged (stored 1) then very little charge flows into the capacitor. To read an individual bit, the sensing circuitry measures the charge stored on the capacitor and determines whether it is 0 or 1. Since capacitors leak charge over time, the information or data eventually fades unless the capacitor charge is refreshed periodically. Examples of memory cells that require periodic refreshing include dynamic random access memory (DRAM) and eDRAM cells.
eDRAM cells with deep trench capacitors or stack capacitors have become a standard feature in most electronic devices requiring cache memory, largely due to increased bit count, lower standby power, and increased stability over static random access memory (SRAM), as well as compatibility with CMOS and FinFET technologies. A major challenge with implementing eDRAM technology is the compatibility of process to logic flow with low enough cost and reasonable complexity of fabricating the trenches in the substrate deep enough or the stacked capacitor high enough to achieve the required capacitance. One way to alleviate the need for deep trenches (or high capacitor stacks) is to increase the unit area capacitance through use of a high-k node dielectric material such as hafnium oxide (HfO2). However, with the increasing demand for greater eDRAM technology, there remains a need for processes that reduce the cost of production of eDRAM cells while increasing the area density and memory performance of the cell. Comparing to high density DRAM array, the embedded DRAM (in logic circuit) can utilize shorter word-line and bitline; so that the cell capacitance (<5 nF) and cell leakage can be relaxed than DRAM (in order to use same process steps logic process, e.g. high-k gate thickness) to achieve lower cost.
A need therefore exists for methodology enabling the low cost production of eDRAM cells with increased area density and performance.